JRepin

cross-posted from: https://lemmy.ml/post/48326251

The Commission is proposing the European Technological Sovereignty Package, marking a change in Europe's approach to its tech ecosystems.

The Commission is putting forward a multi-pronged, comprehensive strategy to achieve technological sovereignty, with initiatives that are interconnected and mutually reinforcing across each stage of the value chain, from chips, to infrastructure, to software, cloud and AI, and in synergy with past and ongoing initiatives such as AI Factories and AI Gigafactories.

This is reflected in four initiatives:

• The Chips Act 2.0 to strengthen the semiconductor ecosystem and supply chain resilience, and boost domestic demand
• The Cloud and AI Development Act (CADA) to unlock the potential AI and cloud, to transform our industrial ecosystems and improve societal outcomes
• The EU Open Source Strategy to reduce dependencies across the entire technology stack
• A Strategic Roadmap for Digitalisation and AI in Energy

cross-posted from: https://lemmy.ml/post/48326251

The Commission is proposing the European Technological Sovereignty Package, marking a change in Europe's approach to its tech ecosystems.

The Commission is putting forward a multi-pronged, comprehensive strategy to achieve technological sovereignty, with initiatives that are interconnected and mutually reinforcing across each stage of the value chain, from chips, to infrastructure, to software, cloud and AI, and in synergy with past and ongoing initiatives such as AI Factories and AI Gigafactories.

This is reflected in four initiatives:

• The Chips Act 2.0 to strengthen the semiconductor ecosystem and supply chain resilience, and boost domestic demand
• The Cloud and AI Development Act (CADA) to unlock the potential AI and cloud, to transform our industrial ecosystems and improve societal outcomes
• The EU Open Source Strategy to reduce dependencies across the entire technology stack
• A Strategic Roadmap for Digitalisation and AI in Energy

The Commission is proposing the European Technological Sovereignty Package, marking a change in Europe's approach to its tech ecosystems.

The Commission is putting forward a multi-pronged, comprehensive strategy to achieve technological sovereignty, with initiatives that are interconnected and mutually reinforcing across each stage of the value chain, from chips, to infrastructure, to software, cloud and AI, and in synergy with past and ongoing initiatives such as AI Factories and AI Gigafactories.

This is reflected in four initiatives:

• The Chips Act 2.0 to strengthen the semiconductor ecosystem and supply chain resilience, and boost domestic demand
• The Cloud and AI Development Act (CADA) to unlock the potential AI and cloud, to transform our industrial ecosystems and improve societal outcomes
• The EU Open Source Strategy to reduce dependencies across the entire technology stack
• A Strategic Roadmap for Digitalisation and AI in Energy

cross-posted from: https://lemmy.ml/post/48174535

AV2 is the next-generation video coding specification from the Alliance for Open Media (AOMedia). Building on the foundation of AV1, AV2 is engineered to provide superior compression efficiency, enabling high-quality video delivery at significantly lower bitrates. It is optimized for the evolving demands of streaming, broadcasting, and real-time video conferencing.

This specification serves as the definitive technical reference for AV2 implementations. It outlines the bitstream syntax, semantics, and decoding processes required to ensure full conformance.

AV2 provides enhanced support for AR/VR applications, split-screen delivery of multiple programs, improved handling of screen content, and an ability to operate over a wider visual quality range.

AV2 is the next-generation video coding specification from the Alliance for Open Media (AOMedia). Building on the foundation of AV1, AV2 is engineered to provide superior compression efficiency, enabling high-quality video delivery at significantly lower bitrates. It is optimized for the evolving demands of streaming, broadcasting, and real-time video conferencing.

This specification serves as the definitive technical reference for AV2 implementations. It outlines the bitstream syntax, semantics, and decoding processes required to ensure full conformance.

AV2 provides enhanced support for AR/VR applications, split-screen delivery of multiple programs, improved handling of screen content, and an ability to operate over a wider visual quality range.

cross-posted from: https://lemmy.ml/post/48171005

This is an abridged version of 2026 RISC-V Market Report and Ecosystem Guide by the SHDgroup, provided at no charge thanks to the support of their sponsors. An unabridged version is also available with over 200 pages and comes with a spreadsheet containing over 300 tables of detailed information. In both versions, the intention is to provide a comprehensive examination of the rapidly expanding semiconductor market, including how it is evolving alongside the concurrent emergence of RISC-V and the influence of AI. The accelerating build-out of data centers for AI inferencing and training and Large Language Models (LLMs) is having a profound impact on semiconductor revenues worldwide. This impact extends to the adoption of the RISC-V ISA in an increasing number of SoCs aimed at including some level of AI functionality in the silicon solution. These impacts also extend to the Semiconductor Intellectual Property (SIP) vendors as they look to accommodate the acceleration of the different Neural Networks being used and EDA Tool vendors as they look to infuse AI functionality into their EDA tools to aid the productivity of silicon designers.

The introduction of RISC-V has fueled extensive CPU architectural exploration, visibly impacting device revenues, unit shipments, design starts, business models and IP licensing revenues on a global basis. The pervasive integration of AI across applications is a primary catalyst in today's semiconductor market. The RISC-V architecture has notably influenced SoC designers and architects and is poised to drive a substantial share of designs, revenues, and unit shipments in the coming years.

cross-posted from: https://lemmy.ml/post/48171005

This is an abridged version of 2026 RISC-V Market Report and Ecosystem Guide by the SHDgroup, provided at no charge thanks to the support of their sponsors. An unabridged version is also available with over 200 pages and comes with a spreadsheet containing over 300 tables of detailed information. In both versions, the intention is to provide a comprehensive examination of the rapidly expanding semiconductor market, including how it is evolving alongside the concurrent emergence of RISC-V and the influence of AI. The accelerating build-out of data centers for AI inferencing and training and Large Language Models (LLMs) is having a profound impact on semiconductor revenues worldwide. This impact extends to the adoption of the RISC-V ISA in an increasing number of SoCs aimed at including some level of AI functionality in the silicon solution. These impacts also extend to the Semiconductor Intellectual Property (SIP) vendors as they look to accommodate the acceleration of the different Neural Networks being used and EDA Tool vendors as they look to infuse AI functionality into their EDA tools to aid the productivity of silicon designers.

The introduction of RISC-V has fueled extensive CPU architectural exploration, visibly impacting device revenues, unit shipments, design starts, business models and IP licensing revenues on a global basis. The pervasive integration of AI across applications is a primary catalyst in today's semiconductor market. The RISC-V architecture has notably influenced SoC designers and architects and is poised to drive a substantial share of designs, revenues, and unit shipments in the coming years.

This is an abridged version of 2026 RISC-V Market Report and Ecosystem Guide by the SHDgroup, provided at no charge thanks to the support of their sponsors. An unabridged version is also available with over 200 pages and comes with a spreadsheet containing over 300 tables of detailed information. In both versions, the intention is to provide a comprehensive examination of the rapidly expanding semiconductor market, including how it is evolving alongside the concurrent emergence of RISC-V and the influence of AI. The accelerating build-out of data centers for AI inferencing and training and Large Language Models (LLMs) is having a profound impact on semiconductor revenues worldwide. This impact extends to the adoption of the RISC-V ISA in an increasing number of SoCs aimed at including some level of AI functionality in the silicon solution. These impacts also extend to the Semiconductor Intellectual Property (SIP) vendors as they look to accommodate the acceleration of the different Neural Networks being used and EDA Tool vendors as they look to infuse AI functionality into their EDA tools to aid the productivity of silicon designers.

The introduction of RISC-V has fueled extensive CPU architectural exploration, visibly impacting device revenues, unit shipments, design starts, business models and IP licensing revenues on a global basis. The pervasive integration of AI across applications is a primary catalyst in today's semiconductor market. The RISC-V architecture has notably influenced SoC designers and architects and is poised to drive a substantial share of designs, revenues, and unit shipments in the coming years.

This month we received the new SpacemiT K3 board. Since its inception, felix86 wasn’t able to run on any of the out-of-order execution hardware, such as the SiFive P550 or the SOPHON SG2042. The former has no vector support, the latter has XTheadVector support. While initially there was consideration for supporting hardware without RVV 1.0 or hardware with XTheadVector, ultimately the decision was that we should instead focus on the future of RISC-V consumer hardware which will have RVV 1.0 due to it being mandatory in the RVA23 profile.

If you watched the felix86 talk at the RISC-V NA summit you might’ve seen a video of gameplay on K1 hardware. You would notice the lack of modern 3D games running on the emulator, because a lot of them would run at less than 5 frames per second. Now that we have much faster hardware, there’s more to show!

TLDW: Huge performance improvements over the K1, and RISC-V performance will only go up from here.

One of the RISC-V SoCs we have been most looking forward to this year is the SpacemiT K3 that features the X100 RISC-V cores that are RVA23 compliant and among the first readily available RVA23 RISC-V platform for running on the likes of Ubuntu 26.04 LTS. In this article is a preview of some very early benchmarks of the SpacemiT K3 with the new Pico-ITX single board computer offering.

The SpacemiT K3 features eight X100 RISC-V cores as well as eight ultra-wide parallel AI computing A100 cores. The X100 cores clock up to 2.4GHz and are RVA23 profile compliant and largely associated as delivering similar performance to the Arm Cortex-A76 cores. The A100 AI cores support INT4 / INT8 / FP8 / FP16 / BF16 and rated for around 60 TOPS API performance. The A100 cores are also among the few RISC-V cores so far available that support RVV 1.0 vector processing.

The SpacemiT K3 Pico-ITX is an interesting little board that pairs the K3 SoC with 10Gb networking, UFS storage, dual M.2 expansion slots, USB Type-C with power delivery and 4K DisplayPort output, and dual channel LPDDR5-6400 memory with 16GB and 32GB configurations offered.

cross-posted from: https://lemmy.ml/post/47499847

BayLibre is proud to announce a successful collaboration with SpacemiT to enable initial functionalities of Android 16 on the SpacemiT K1 (RISC-V RVA22 + RVV 1.0) System-on-Chip (SOC). This achievement marks a significant step toward validating and accelerating Android enablement on high-end RISC-V platforms.

The main objective of this project was to validate the feasibility of porting modern Android to recent, high-performance RISC-V platforms. Furthermore, this work serves as crucial preparation for Android enablement on upcoming RISC-V profile RVA23 SOCs, as much of the effort and code will be directly reusable.

BayLibre is proud to announce a successful collaboration with SpacemiT to enable initial functionalities of Android 16 on the SpacemiT K1 (RISC-V RVA22 + RVV 1.0) System-on-Chip (SOC). This achievement marks a significant step toward validating and accelerating Android enablement on high-end RISC-V platforms.

The main objective of this project was to validate the feasibility of porting modern Android to recent, high-performance RISC-V platforms. Furthermore, this work serves as crucial preparation for Android enablement on upcoming RISC-V profile RVA23 SOCs, as much of the effort and code will be directly reusable.