The advantages that we'll see come from the implementation more than the spec, but having an open standard for the ISA allows more companies to make implementations and to innovate.

The true benefits will be ~10 years in, when RISCV chip designers are more experienced and have had time to innovate and build good IP blocks.

E.g. companies that make ARM SoCs are pick'n mix'ing IP from ARM, and adding their own special sauce on top. The future in RISCV comes from having many companies that compete to make intercompatible IP, which hardware vendors like Qualcomm and Rockchip can then licence to make SoCs out of.

There is benefit to RISCV, over ARM but mostly that comes down to:

• not having legacy compatibility to maintain.
• having a frozen spec that is less likely to slowly get feature creep like x86 & ARM.
• having hindsight for things like vector extension implementations & macro-op fusion.

It's predominantly the first one. They have made a few unique design decisions, but is a fairly conservative "boring" RISC design. The only thing remarkable I can think of of the core ISA is the fact that they have no conditional status registers (no NZVC bits), so you have to kind of combine conditions and branches together, but that's not exactly unprecedented (MIPS did something similar).

In the ISA extensions, there is still some instability and disagreement about the best ISA design for some parts. Just the fact that RISC-V is going to have both SIMD and Vector instructions is a bit unique, but probably won't make a huge difference.

But it's a fairly boring RISC design which is free and open and without any licensing hoops to jump through, which is the most interesting bit.