this post was submitted on 25 Jan 2025
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pretty much the title.

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[–] chris@lemm.ee 23 points 2 weeks ago (1 children)

Is there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.

[–] deur@feddit.nl 20 points 2 weeks ago* (last edited 2 weeks ago) (2 children)

In principle it's just "slimmer ARM". RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.

Think lots of registers, a fun zero register that is always zero, and memory mapped IO.

[–] mvirts@lemmy.world 5 points 2 weeks ago (2 children)

I for one think we need a register for each unsigned integer, why is zero so special? :P

Or if we can't get that, at least every power of 2 and power of 2 minus 1.

Maybe I can submit a proposal for risc-VI 🤣

[–] PetteriPano@lemmy.world 9 points 2 weeks ago

Maybe I can submit a proposal for risc-VI 🤣

No need! You can make your own custom extension! If the silicon doesn't support it, then you can provide firmware to emulate it.

[–] porl@lemmy.world 5 points 2 weeks ago

I think a register for each of the primes should be enough.

[–] caseyweederman@lemmy.ca 3 points 2 weeks ago (1 children)

ARM is also reduced-instruction set but I don't know how they differ. Is the instruction set somehow more reduced?

[–] MonkderVierte@lemmy.ml 3 points 2 weeks ago

Aren't they more like a hybrid instruction set and architecture?