Hardware

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A community for news and discussion about the hardware side of technology. Questions and support posts are also welcome, so long as they are relevant to hardware and interesting technologies therein.


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founded 2 years ago
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You can also buy it as a DIY kit, or simply reference the components list and instructions, and use the firmware, drivers, and software shared.

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'Black Pearl solid silver conductors drawn in diamond coated dies and insulated with virgin FEP dielectric' doesn't help.

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There are levels to SSD clones.

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A $25 IPS panel gives this old Lenovo laptop a decisive visual upgrade

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Amazon introduced ads into their line of smart displays. Luckily, hackers have found a way to liberate a few of them.

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RVA23 profile of RISC-V marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on.

RVA23 doesn’t force scalar execution to become deterministic. It simply makes determinism viable because the scalar side is no longer responsible for throughput. The vector unit handles the parallel work explicitly, and the scalar core becomes a coordinator that can be simple, predictable, and low‑power without sacrificing performance.

To understand why this shift matters, it helps to recall how thoroughly speculative execution came to dominate high-performance CPU design. It delivered speed, but at increasing cost—in power, complexity, verification burden, and security exposure. RVA23 does not reject speculation. Instead, it restores balance. It acknowledges that predictable, vector-driven parallelism is now a credible, mainstream path for performance growth.

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Worse than Biden's AI Diffusion Rule?

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Hard drives hit an important 44TB capacity milestone.

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LILYGO has released two new ESP32-based products: the T-Halow P4, a compact development board built around Espressif’s ESP32-P4 RISC-V SoC with integrated Wi-Fi HaLow support, and the T5 E-Paper S3 Pro Lite, a 4.7-inch ESP32-S3 e-paper device positioned as a simplified version of the Pro model introduced in 2024.

The T-Halow P4 is built around the ESP32-P4, which features a dual-core 32-bit RISC-V processor running at up to 360 MHz alongside a 40 MHz low-power RISC-V coprocessor. The board includes 16MB of external NOR flash and 8MB of PSRAM.

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HMD's new phone is purpose-built for military personnel, law enforcement agents, first responders, and infrastructure operators who find themselves in super hot or cold environments on the job. It's all about essential features for tough conditions with this one – starting from how you interact with it.

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This could go on for another 10 years.

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The Belgian research institute imec opened the NanoIC pilot on Monday. This line, an investment of 2.5 billion euros, is intended to develop

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