this post was submitted on 10 Dec 2025
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RISC-V

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RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

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Linux 6.19 For RISC-V Brings Parallel CPU Hotplugging, Zalasr Ratified ISA Support (www.phoronix.com)
submitted 2 months ago by cm0002@toast.ooo to c/riscv@programming.dev
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The RISC-V CPU architecture changes have been merged for the in-development Linux 6.19 kernel.

With this new kernel RISC-V now supports CPU hot-plugging in parallel for secondary CPU cores. Secondary CPU cores can now be brought up asynchronously with the "HOTPLUG_PARALLEL" kernel feature now being supported on RISC-V for more quickly bringing up multiple CPU cores besides the primary CPU0. The CPU hot-plugging support particularly with RISC-V SoCs is primarily about dynamic enabling/disabling of CPU cores while the system is running rather than needing to handle their bring-up sequentially.

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