RISC-V

103 readers

10 users here now

RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

riscv.org

Youtube

Matrix space

founded 4 months ago

MODERATORS

cm0002@programming.dev

cm0002@lemmy.world

cm0002@lemdro.id

Picolibc Picks Up RISC-V Improvements, Hexagon Support & Better POSIX Compliance (www.phoronix.com)

submitted 3 weeks ago by cm0002@suppo.fi to c/riscv@programming.dev

0 comments fedilink hide all child comments

Keith Packard published Picolibc 1.8.11 on Monday as the newest release for his C library designed for embedded 32-bit and 64-bit platforms. Picolibc continues tacking on new CPU architecture support and other features for this project that started out as a conglomeration of the Newlib and AVR Libc C library codebases.

Picolibc 1.8.11 adds support for Qualcomm's Hexagon DSP architecture. Also on the CPU side are a number of RISC-V improvements like supporting the "-mlarge" model in Assembly code and improved RISC-V vector unit in the start-up code. Over on the ARM side is also improved ARM32 A-Profile operation in Thumb state.

no comments (yet)

sorted by: hot top controversial new old

there doesn't seem to be anything here